The present invention relates to a random access memory (RAM) having multiple-bit input/output (I/O) terminals, and in particular to a RAM which can operate in a mode in which reading through designated I/O terminals is enabled or permitted while reading through other I/O terminals is inhibited.
An example of conventional RAM having multiple-bit I/O terminals that is disclosed in Japanese Patent Kokai Publication No. 179984/1985 will first be described with reference to FIG. 2.
The RAM comprises a memory cell array 3 which comprises a matrix of memory cells 3a formed of a MOS transistor and connected to a plurality of word lines WL and a plurality of pairs of bit lines BL intersecting the word lines. Sense amplifiers not shown are connected to the respective pairs of bit lines to sense and amplify data read from the memory cells.
The illustrated RAM is of a multiple-address type using a row control signal RAS, and a column control signal CAS. A row address buffer 1 is controlled by the row control signal RAS to read a row address from the address signals A0, A1, . . . , An which are supplied from outside of the RAM, and its output is connected to the memory cell array 3, via a row address decoder 2 which decodes the output of the row address buffer 1.
A column address buffer 4 is controlled by the column control signal CAS to read a column address from the address signals A0, A1, . . . , An, and its output is connected to the memory cell array 3, via a column address decoder 5 and a transfer gate circuit 6. The column address decoder 5 decodes the output of the column address buffer 4. The transfer gate circuit 6 is formed of a plurality of pairs of switches for selectively connecting the pairs of bit lines BL with four pairs of I/O bus lines 7.sub.0 to 7.sub.3, on the basis of the output of the column decoder 5. As the pairs of switches are selected by the column address, the pairs of bit lines connected to the selected switches are connected to the I/O bus lines, and in this way "selected". Since there are four pairs of I/O bus lines, four of the pairs of bit lines are selected at a time and connected to the I/O bus lines.
Connected to the I/O bus lines are data amplifiers 8.sub.0 to 8.sub.3, and I/O buffer circuits 9.sub.0 to 9.sub.3. Connected to the I/O buffer circuits 9.sub.0 to 9.sub.3 are I/O terminals 10.sub.0 to 10.sub.3 for input and output of write data and read data.
The operation of writing of data in the memory cell array 3 and reading of data from the memory cell array will now be described.
For reading data from the memory cell array 3, address signals A.sub.0, A.sub.1, . . . , A.sub.n are supplied from outside of the RAM to the row address buffer 1 and the column address buffer 4. The row address buffer 1 controlled by the row control signal RAS reads the row address from the address signals A.sub.0, A.sub.1, . . . , A.sub.n, and the row address is decoded by the row address decoder 2, so that one of the word lines WL is activated. Then data stored in the memory cells 3a connected to the activated word line WL are output to the pairs of bit lines BL. The data read onto the pairs of bit lines BL are sensed and amplified by the sense amplifiers, not shown.
The column address buffer 4 controlled by the column control signal CAS reads the column address from the address signals A.sub.0, A.sub.1, . . . , A.sub.n, and the column address is decoded by the column address decoder 5. Depending on the result of the decoding, the four pairs of the switches in the transfer gate circuit 6 are selected and turned on, and four pairs of bit lines BL thus selected (connected to the selected switches) are connected to the four pairs of I/O bus lines 7.sub.0 to 7.sub.3, and the data on the four pairs of the bit lines BL are transferred to the I/O bus lines 7.sub.0 to 7.sub.3. The data on the I/O bus lines 7.sub.0 to 7.sub.3 are amplified by the data amplifiers 8.sub.0 to 8.sub.3, and output via the I/O buffer circuits 9.sub.0 to 9.sub.3, and the I/O terminals 10.sub.0 to 10.sub.3, to outside of the RAM.
For writing data, the data to be written are supplied from outside of the RAM to the I/O terminals 10.sub.0 to 10.sub.3. The data are then read by the I/O buffer circuits 9.sub.0 to 9.sub.3, and sent to the I/O bus lines 7.sub.0 to 7.sub.3. Then, in accordance with the output of the column decoder 5, four pairs of the switches in the transfer gate circuit 6 are selected and turned on and the four pairs of the selected bit lines BL are connected to the four pairs of the I/O bus lines 7.sub.0 to 7.sub.3. The data is written in the memory cells 3a connected to the selected word line WL and the four pairs of the selected bit lines BL.
FIG. 3 is a circuit diagram showing the I/O buffer circuit 9.sub.0 of FIG. 2. The other I/O buffer circuits 9.sub.1 to 9.sub.3 have an identical configuration.
The I/O buffer circuit 9.sub.0 comprises an input buffer 21 connected between the I/O terminal 10.sub.0 and the I/O bus lines 7.sub.0, and an output buffer 22 connected between the I/O bus lines 7.sub.0 and the I/O terminal 10.sub.0. An input control transfer gate 23 connects or disconnects the input buffer 21 and the I/O bus lines 7.sub.0. The transfer gate 23 is turned on and off by the output of the write inhibit register 24. The write inhibit circuit 24 is formed of a write inhibit sensing circuit 24A and a buffer 24B.
FIG. 4 is a circuit diagram showing an example of control signal generating circuit for generating various control signals used in FIG. 2 and FIG. 3.
The control signal generating circuit 30 comprises an inverter 31.sub.1 which receives the row control signal RAS and produces a signal RAS (inversion of RAS), which is passed through buffers 32.sub.1, 32.sub.2, 32.sub.3 and 32.sub.4, in turn, and signals RAS.sub.1, RAS.sub.2, RA and SE are obtained at the outputs of the respective buffers. The signal RAS is also inverted by an inverter 31.sub.2 and then passed through a buffer 32.sub.5, and a precharge signal PX.sub.0 and another precharge signal PX.sub.1 are obtained at the outputs of the inverter 31.sub.2 and the buffer 32.sub.5.
An AND gate 33.sub.1 determines the logical product of a word line activation signal RA and the inversion of the column control signal CAS, and a signal CAS is obtained at the output of the AND gate 33.sub.1.
An inversion of the column control signal CAS is input to a NAND gate 33.sub.6, and its output signal CAS4 and a write control signal WE are input to a NAND gate 33.sub.5. The output signal CAS.sub.3 of the NAND gate 33.sub.5 is input to the NAND gate 33.sub.6, and to a NAND gate 33.sub.3. The output signal CAS.sub.2 of the NAND gate 33.sub.3 and the signal CAS are input to a NAND gate 33.sub.2, whose output signal CAS.sub.1 is input to the NAND gate 33.sub.3, and to an inverter 33.sub.4. An output enable control signal OE1 is obtained at the output signal of the inverter 33.sub.4.
The signal CAS is inverted by an inverter 34, and is passed through a buffer 33.sub.7, and a precharge signal PY.sub.0 and another precharge signal PY.sub.1 are obtained at the outputs of the respective circuits.
An AND gate 35 determines the logical product of the inversion of the precharge signal PY.sub.1 and the inversion of the write control signal WE, and produces a signal W.sub.0, which is passed through a buffer 36, and a signal W1 is obtained at the output of the buffer 36.
Referring again to FIG. 3, REF in the input buffer 31 denotes a reference signal, WCA.sub.0 in the write inhibit register 24 is an output signal of the inhibit sensing circuit 24A, and WCB.sub.0 denotes an output signal of the buffer 24B.
FIG. 5 is a timing chart showing the operating of the circuits of FIG. 2 and FIG. 3. The operation of the circuit of FIG. 3 is first described with reference to FIG. 5.
During reading (read cycle RC in FIG. 5), the input buffer 21 is inactive because the signal W1 is kept Low throughout each read cycle. The output signal WCA.sub.0 of the write inhibit sensing circuit 24A is inactive because the write control signal WE is kept High, and the output signal WCB.sub.0 is therefore kept Low throughout each read cycle. As a result, the input control transfer gate 23 is off. Read data of the selected pairs of bit lines BL is output to the I/O bus lines 7.sub.0, and output via the output buffer 22 and the I/O terminal 10.sub.0.
During writing (write cycles WC.sub.0 and WC.sub.1 in FIG. 5), the write inhibit sensing circuit 24A identifies the write cycle on the basis of the write control signal WE after the falling edge of the column control signal CAS. The write inhibit sensing circuit 24A also determines whether writing is to inhibited on the basis of the write control signal WE and the level of a signal applied from outside of the RAM to the I/O terminal 10.sub.0 at the falling edge of the row control signal RAS. The output signal WCA.sub.0 is passed through the buffer 24B, and its output WCB.sub.0 turns on the input control transfer gate 23 to permit writing of data.
That is, if, at the time of the falling edge of the row control signal RAS, the write control signal WE is Low (Active) and the signal applied to the I/O terminal 10.sub.0 is also Low (Active), as shown in the write cycle WC.sub.0 in FIG. 5, the output signal WCA.sub.0 goes High, which is passed through the buffer 24B. The output WCB.sub.0 of the buffer 24B, which therefore goes High turns on the transfer gate 23. As a result, the output of the input buffer 21 is connected to the I/O bus lines 7.sub.0, and normal writing operation is enabled.
If, at the time of the falling edge of the row control signal RAS, the signal applied to the I/O terminal 10.sub.0 is made High, as shown in the write cycle WC.sub.1 in FIG. 5, then the output signal WCB.sub.0 of the buffer 24B is maintained Low. As a result, the transfer gate 23 is off and the output of the input buffer 21 is not connected with the I/O bus lines 7.sub.0. In this state, even if a write data is applied to the I/O terminal 10.sub.0 during the period when the CAS is Low, writing of data onto the I/O bus lines 7.sub.0 (and hence in the memory cell 3a) is inhibited.
FIG. 5 also shows the signal applied to another I/O terminal 10.sub.1 and the output signal WC.sub.1 of the write inhibit register 24 in another I/O buffer circuit 9.sub.1 corresponding to the I/O terminal 10.sub.1. It will be seen that in the write cycle WC.sub.0 when writing through the I/O buffer circuit 9.sub.0 is permitted, writing through the I/O buffer circuit 9.sub.1 is inhibited. In the write cycle WC.sub.1 when writing through the I/O buffer circuit 9.sub.1 is permitted, writing through the I/O buffer circuit 9.sub.0 is inhibited. In this way, the RAM can operate in a write-per-bit mode, in which writing is permitted through only the designated ones of the I/O buffer circuits 9.sub.0 to 9.sub.3 while writing through other I/O buffer circuits is inhibited.
Thus, by the function of the write inhibit register 24 and the transfer gate 23, control for independent writing of each of the I/O terminals 10.sub.0 to 10.sub.3 is realized without sacrificing the normal memory function.
In the RAM of the above configuration, when a special timing, such as the one for read-modify-write, is adopted for the purpose of enhancing the versatility of the system, unnecessary data output is performed onto the I/O terminals 10.sub.0 to 10.sub.3 which are not conducting the writing operation. As a result, the power consumption at the time of output is increased.